industry

Industry experience applying graph machine learning and topology to semiconductor data.

Software Engineer Intern, Intel, Oregon May – Aug 2026

  • Built a graph pipeline that extracts schematic topology from chip layout files.
  • Used subgraph embeddings to classify analog, digital and fill devices.
  • Worked with design-for-manufacturing (DFM) engineers to fit the tools into their workflow.

Graduate Technical Intern, Intel May – Aug 2025

  • Ran spatial pattern analysis on chip layer images with KLayout and Python.
  • Trained graph neural networks to classify similar layout patterns.
  • Brought machine learning into yield-analysis workflows.

Skills

  • Languages: Python, R, SQL
  • Methods: graph neural networks, graph transformers, topological data analysis, persistent homology, Dynamic Mode Decomposition
  • Libraries: PyTorch, PyTorch Geometric, NetworkX, GUDHI, scikit-learn
  • Tools: Git, Linux, KLayout, LaTeX